1. Technical Field
Embodiments of the present disclosure generally relate to an input/output (I/O) line test device and a method for controlling the same, and more particularly to a technology for testing a base die having no cell using various patterns.
2. Related Art
Recently, semiconductor devices having semiconductor chips that are stacked and using through silicon via (TSV) have been researched and developed. For example, multi-chip packages are one representative example of a multi-chip package in which plural semiconductor chips are vertically stacked and designed to transmit/receive signals using a through silicon via (TSV). These multi-chip packages have been recently developed and used.
Electronic industries have been rapidly developed to implement low-priced products having lighter weights, smaller sizes, higher speeds, multifunctional abilities, higher performances, and greater reliability. One of the important technologies used to attain goals related to product designs is to use a multi-chip stacked package technology or a system-in-package technology. The multi-chip stacked package technology or the system-in-package technology may use through silicon via (TSV).
The multi-chip stacked package technology or the system-in-package technology may enable functions of plural unit semiconductor devices to be performed in one semiconductor package. Although the multi-chip stacked package or the system-in-package may be greater in thickness than a general single-chip package, the multi-chip stacked package or the system-in-package is very similar in planar size to the single-chip package. As a result, the multi-chip stacked package and the system-in-package have been widely used in mobile products having higher performances and smaller sizes, for example, mobile phone, laptops, memory cards, mobile camcorders, etc.
When fabricating the semiconductor package, a testing process may be performed to determine whether the semiconductor device operates normally. Using this testing process while fabricating may result in an increase in production efficiency. The testing process of the semiconductor device may include applying an electric signal to the pad of the semiconductor device, and determining whether output data is normal.
The semiconductor devices (e.g., DRAMs) may write various data in a cell, read the various data patterns from the cell, and thus test input/output (I/O) lines. If the I/O lines are connected to each other, opposite data may be written only in a small number of I/O lines and then may be read from the small number of I/O lines, such that it may be possible to determine the influence of such connection between the I/O lines. In addition, a margin between each pin and the I/O lines may be tested by reading previously written data.
However, when at least two chips are stacked to perform one operation in the same manner as in a high bandwidth memory (HBM), the at least two chips must be tested in different ways.
That is, if two different chips are combined and integrated with each other, all the I/O lines can be tested. However, when testing each chip, only one input line and output line can be tested for each chip, resulting in a limitation in chip testing.